Multiplexer-module: introduction

This is probably the least complex module in the CPU - it contains only combinational logic (see a previous section), and only a few gates per bit.
This section shows how a 1-bit multiplexer can be constructed out of basic gates. An N-bit multiplexer can be constructed by placing multiple 1-bit multiplexers in parallel.
Furthermore, truth-tables are introduced as a convenient way to describe the functional behaviour of gates.
Selecting 1 out of 2 bits

As seen from the outside, a 1-bit multiplexer is the same as an N-bit one (shown in the section about the CPU's subsystems), except that its output and both its inputs are only 1 bit wide.
There are several ways to construct a 1-bit multiplexer; one such way is to use 3 NAND-gates and an inverter, as shown here.
Recall that the NAND-function's output is high, unless both its inputs are high.
This NAND-behaviour can be written in the form of a truth-table. In this case, the leftmost 2 columns represent inputs A and B to the NAND-function, and the rightmost column represents the function's output:
A B | A NAND B | 0 0 | 1 0 1 | 1 1 0 | 1 1 1 | 0
Likewise, for the given 1-bit multiplexer, a similar truth-table exists, in which the outputs of the top-left and bottom-left NAND-gates are named out_TL and out_BL respectively.
These intermediate outputs are then written as functions of A, B and the select-input:
sel A B | out_TL out_BL | 0 0 0 | 1 1 0 0 1 | 1 1 0 1 0 | 1 0 0 1 1 | 1 0 | 1 0 0 | 1 1 1 0 1 | 0 1 1 1 0 | 1 1 1 1 1 | 0 1
(The blank line is added for readability.)
The table can be extended with output Y of the right-most NAND-gate, being a function of its inputs out_TL and out_BL:
sel A B | out_TL out_BL Y | 0 0 0 | 1 1 0 0 0 1 | 1 1 0 0 1 0 | 1 0 1 0 1 1 | 1 0 1 | 1 0 0 | 1 1 0 1 0 1 | 0 1 1 1 1 0 | 1 1 0 1 1 1 | 0 1 1
Note that final output Y can be written as:
Y = ( ( NOT sel ) AND A ) OR ( sel AND B )
Or in words: "if sel is low, take A, else take B".
This is exactly the desired behaviour.
Array of 1-bit multiplexers
Forming an N-bit multiplexer out of several 1-bit multiplexers is trivial: N 1-bit multiplexers are placed in an array, all sharing a single select-input.
All inputs A together form one N-bit input, and all inputs B together form the other N-bit input. All outputs Y together form the N-bit output.
Although low in complexity, 2 inputs and 1 output per bit quickly add up, when looking at module pin-count. That's why each multiplexer-module is only 5 bits wide.
It's easy to combine several such modules to form a 16-bit multiplexer, needed in the Qibec CPU.