Address-latch: introduction

The address-latches are not really part of the CPU's design, and only serve to stabilise the program-counter output.

For practical reasons (maximum module pin-count), the two 16-bit address-latches in the CPU are implemented using four 8-bit address-latch modules.

This section shows how a clearable data-latch can be constructed out of an SR-latch, and an address-latch out of these clearable data-latches.

Creating a clearable data-latch out of an SR-latch

Like aforementioned submodules, a 16-bit address-latch can be constructed from 1-bit gates.

In this case, the appropriate building-block is a clearable data-latch, and looks much like the data-latch used to read and invert a data-bit in RAM.

Compared to the data-latch used earlier, the clearable latch used here has a clear-input, and lacks the inverted Q-overline output.

The clear-input is used to set latch-output Q low when the CPU is being reset through its reset-input.

Recall from the section about the CPU's subsystems that the address-latches are positioned before the CPU's program-counter output. (Or rather, they form the program-counter.)

The desired behaviour when resetting the CPU, is to reset the program-counter to zero. This way, the CPU would start execution at the beginning of the program when reset is released.

One way to construct a clearable data-latch is to use an SR-latch as starting-point, and adding D-, enable- and clear-inputs as shown here.

This way of clearing the latch-output works fine as long as the clear-input is released before the enable-input is released.

(If interested, apply values at the D-, clear- and enable-inputs, trace the wires and apply the rules of the NAND- AND- and NOR-function to see why this is the case.)

The timing-module in the Qibec CPU ensures that the enable- and clear-input are never active simultaneously, avoiding this potential problem.

Creating an address-latch out of clearable data-latches

Creating a 16-bit address-latch from individual 1-bit clearable latches is trivial: all 1-bit latches would share their clear- and enable-inputs, all D-inputs together would form the address-latch input, and all Q-outputs together would form the address-latch output.