# Address-increment unit: introduction

The address-increment unit takes as input a 16-bit address, and has as output the address incremented by one. Therefore, this module basically adds 2 numbers, one of these numbers being a constant "1".

Like the multiplexer discussed earlier, this is a pure combinational block (its output only depends on its input, not on its input-history).

A combined block known as a "half adder" is introduced, using a somewhat different explanation than commonly seen. The complete address-increment unit can then be constructed by placing a number of these adders in cascade.

# Adding 2 bits

In the previous section about binary numbers, binary arithmetic was shown to be very similar to decimal arithmetic.

Consider 2 binary numbers being added, with one of these numbers being "1":

```     carried :      11

number A :    01011
constant "1" :    00001
------- +(bin)
sum Y :    01100        ```

Columns are added from right to left, just like with a pen-and-paper decimal addition. The sum is called Y, a common output-indicator for logical blocks.

The address-increment unit does eactly this: add a number A (address) and a constant "1".

It would be convenient to implement this behaviour using an array of identical "1 bit adding" blocks. However, the bits forming the constant "1" are an inconvenience: the rightmost bit in this number is binary "1", and all other bits are "0".

To get rid of this constant, the above addition can be rewritten by adding a fake carried bit above the rightmost column. (Fake in that the rightmost column was the first addition to be performed, so there wouldn't be an actual carried bit from a previous addition yet.)

Furthermore, because in this new situation the fake carried bit is added as well, the constant "1" can be reduced to "0" to give the same sum Y:

```     carried :      111

number A :    01011
constant "0" :    00000
------- +(bin)
sum Y :    01100        ```

This addition can be simplified by removing the constant "0":

``` carried :      111
number A :    01011
------- +(bin)
sum Y :    01100        ```

This behaviour can be implemented using an array of 1-bit adders, that each have:

• a 1-bit input CI ("carry in")
• a 1-bit input A
• a 1-bit output Y, being the sum modulo 2 of adding A and CI
• a 1-bit output CO ("carry out"), being 1 if and only if both A and CI are 1

Alternatively, a truth-table describing this behaviour can be given:

```CI   A   |   Y   CO
|
0    0   |   0   0
0    1   |   1   0
1    0   |   1   0
1    1   |   0   1 ```

One possible implementation of such a block is shown here.

In practice, because of the particular way transistors are used within the Qibec CPU ("RTL" - Resistor-Transistor Logic) , NOR- and NAND-gates are more convenient to construct than AND- and OR-gates.

However, recall that a NAND-gate is basically an AND-gate followed by a NOT-gate. Likewise, an AND-gate can be constructed by using a NAND-gate with a NOT-gate behind it.

# Adding N bits

As with the N-bit multiplexer, creating an N-bit increment-unit out of 1-bit adders becomes trivial, by placing N 1-bit adders in cascade.

The CO-output of each stage is connected to the CI-input of the next stage. The CO-output of the last stage (most significant bit) is simply discarded, and the CI-input of the first stage is set to a fixed "1".

(This "1" represents the fake carried bit, discussed earlier.)