Basic principle: introduction
The Qibec CPU belongs to a class of systems called One Instruction Set Computer (OISC).
This means that only one instruction is available, and to execute a program, the CPU repeatedly executes this instruction.
As an introduction, this section looks at the CPU as seen from the outside. Subsequent sections deal with its inner workings.
A crash-course in computing
Below follows an introduction of some computer-related terms.
First, the term "memory" in this context means "a place where items are stored", and can be regarded as a filing-cabinet.
A memory can hold a finite number of items - say N. Each item within a memory sits at a location, or "address" within that memory - in this case, addresses can range from 0 to N, exclusive. An address can thus be used to store and retrieve specific items from a memory.
One type of memory is used to hold a program - another is used to hold temporary data.
The type of memory to hold the program is typically Read-Only Memory ("ROM"), while memory to hold temporary data is Random Access Memory ("RAM") - that is, readable/writable memory.
Subsequent sections discuss ROM and RAM in more detail.
A "program" for a computer is essentially a recipe to tell it what to do, and consists of instructions. "Executing a program" basically means performing these instructions, in order to manipulate the contents of the data-memory in a desired way.
(For example, a very simple program could state "for each address in the data-memory, set the data-item at that address to zero". Executing the program would thus clear the data-memory.)
Typically, a computer-system consists of at least a CPU (processor), a program-memory (ROM), and a data-memory (RAM).
It is useful to understand what the CPU looks like from the outside. Its behaviour can then be described in terms of interaction with the outside world.
For any system, "I/O (input/output) channels" are the means of communication with its surroundings. (In this respect, human "systems" have ears as input-channel, and a mouth as output-channel.)
The Qibec CPU has only 3 such I/O-channels:
- a program-counter ("PC") output, holding the address of the current instruction
- a branch-input, holding the address of an arbitrary instruction
- a data-channel, which holds the data that is currently being manipulated
Depending on the direction of the channel, the CPU writes to the outside world (in case of the program-counter output), or reads what the outside world has written (in case of the branch-input). The data-channel alternates between input and output.
(Apart from these 3 I/O-channels, the CPU has some control-lines, discussed in following sections.)
During each instruction
Program-instructions are executed one at a time, in what are called "instruction-cycles". Each instruction takes 1 cycle to execute. During each instruction-cycle, the I/O-channels listed above are manipulated as follows.
First, the CPU inverts the data-channel (1 becomes 0, and 0 becomes 1), and then reads its value.
If the value of this 1-bit channel is 1 after inversion, the program-counter is simply incremented by 1.
However, if the value of this data-bit is 0 after inversion, the program-counter is set to the address coming in on the branch-channel.
During the next instruction-cycle, the data-channel is again inverted, then read, and so on.
How this mechanism can be used to form a computer-system is discussed in following sections.
Because of the 1-bit width of the data-channel, it's impossible to manipulate multiple data-bits at the same time. Most modern CPUs manipulate 8, 16, 32 or 64 data-bits simultaneously.
Furthermore, the data-channel is inverted every instruction-cycle.
This means that, in order to make decisions based on the state of the data-memory, that data-memory has to be changed. It's impossible to simply read a data-bit without altering it.
Other flaws (or features) will become apparent when discussing the CPU/memory interface, and when talking about programming.