Architecture

Compared to most regular CPUs, Qibec has a very simple architecture.

For instance, there is no ALU (Arithmetic Logic Unit), no pipeline (although the clock-signal is divided into phases), no instruction-decoding (because only 1 instruction exists), and there are no real registers.

The CPU consists of transistors - about 650 of them in total, most of which are simply "copy/pasted" to implement the address-bus.

Qibec's actual core (somewhat similar to an ALU in a regular CPU) has only 8 transistors.

In this chapter...

• First, the basic principle of operation is given, in terms of interaction with the outside world. Some of the features, quirks and shortcomings of the CPU will be shown.

• This is followed by an introduction of the CPU's subsystems, each performing a specific part of instruction-execution. This section takes a look at what goes on inside the CPU.

• The way in which the address- and data-bus are used, is quite unlike other regular CPUs - Qibec itself is totally unaware of RAM-addressing (and yet, manipulates RAM).

• During each cycle, sub-parts of the CPU work in turn to read and write RAM, latch address-data, and update outputs. In order to do this, the external clock-input is divided into different phases.