Address- and data-bus: introduction

This section covers the interface between the CPU and external memory.

Some differences between Qibec and a classic system with address- and data-bus are discussed. For instance, this CPU cannot address RAM directly, and yet, uses RAM.

Finally, a complete system with CPU, ROM and RAM is suggested.

ROM for storing a program

As stated before, a computer-memory can be regarded as a filing-cabinet.

A data-item can be stored and retrieved by its address, indicating the item's location within the memory.

In a Read-Only Memory (ROM), items can not be modified, only retrieved. An actual ROM has items placed at appropriate addresses during manufacturing.

A ROM is therefore suited for storing a program-image to be used by a CPU. In this case, each data-item in the ROM serves as a program-instruction. During each instruction-cycle, the CPU reads a program-instructions at a specific ROM-address.

The ROM's interface to the outside world is quite simple: an address goes in, and the corresponding data at that address comes out. Both the address and the data can be regarded as binary numbers.

In case of the Qibec CPU, a ROM with an address-width of 16 bits is used, and a suggested data-width of 32 bits. (This ROM can store 65536 data-items of 32 bits each. A program can therefore contain 65536 instructions, at most.)

RAM for storing temporary data

A Random Access Memory (RAM) is used for storage of temporary data. It can be regarded as a scratch-pad where the CPU writes and reads its data.

So, contrary to a ROM, a RAM is both readable and writable, and therefore needs not be written during manufacturing - the CPU itself can do that.

The interface of a RAM resembles that of a ROM, with the exception that a RAM also has a write-input.

When this write-input is low (inactive), the RAM behaves like a ROM: the CPU supplies an address, and the RAM supplies the data-item stored at that address.

However, When the write-input is high (active), the CPU supplies both an address and a data-item, and the RAM writes the supplied data-item at the indicated address.

The suggested number of data-items in a RAM to be used by the Qibec CPU is also 65536. The width of each data-item is 1 bit.

The term "data"

In the above text, ROM and RAM were discussed as generic building-blocks. Both use the concepts of "address" (the location of something) and "data" (something at a specific location).

The term "data" is meaningless. In the remainder of this section, it is given meaning and name, depending on the context in which it is used.

For example, a generic ROM takes as input an address, and outputs the corresponding data at that address. As far as the ROM is concerned, this data has no meaning yet.

However, that ROM-data could be used (interpreted) as a numeric value, part of a graphical image, or even as another address.

For example, when used by the Qibec CPU, the ROM's data is given the meaning of branch-address. Or, when connected to a RAM, the ROM's data is given the meaning of RAM-address.

Classic address- and data-buses

In computer-systems, the term "bus" loosely means a junction where different subsystems are connected.

Without going into much detail, a subsystem connected to a bus could place information (a binary number, say) onto the bus, and other subsystems could then use that information.

A classic system containing CPU, RAM and ROM would have 2 buses: an address-bus and a data-bus. Each of these 3 subsystems would be connected to both buses.

On the address-bus, binary numbers representing addresses would be passed around, while on a data-bus, binary numbers representing data-items would be transfered.

For example, in order to read a program-instruction, the CPU would place the ROM-address of the instruction onto the address-bus. The ROM would then place the requested data-item (representing the program-instruction) onto the data-bus. Finally, the CPU would read this program-instruction from the data-bus for further processing.

To write data to RAM, a classic CPU would place the data's RAM-address onto the address-bus, and the data to be written onto the data-bus. The RAM would then write the supplied data at the supplied address.

(To determine to which memory - RAM or ROM - each such operation applies, some sort of selection-mechanism would have to be used, not further discussed here.)

Note that in this classic example, the information on the data-bus is always written by either the CPU, RAM or ROM. In other words, at any time, the contents of the data-bus is supplied by one and only one subsystem.

Split, or dual data-bus

The Qibec CPU has a fairly normal address-bus formed by its program-counter output, where it outputs a program-address to the ROM.

However, instead of a single data-bus, it actually has two - or rather, its data-bus is split up into two parts.

The first part is formed by the CPU's branch-input. During each instruction-cycle, the CPU expects the ROM to supply a 16-bit branch-address at this input.

The remaining part of the data-bus is formed by the 1-bit data-channel. During each instruction-cycle, the CPU expects a data-bit in RAM to be made available here, which it reads, and then inverts. The CPU's write-output - labeled W - determines whether to read (low) or write (high).

Thus, 16 bits of the CPU's data-bus are connected to the ROM, and the remaining bit is connected to the RAM.

Complete system with CPU, ROM and RAM

Because of this dual data-bus, a complete system with Qibec CPU, ROM and RAM looks a bit different than the classic setup given earlier.

The suggested setup with CPU, ROM and RAM is shown here.

Note that the use of ROM is more or less the same as in a classic system: the CPU outputs an address through its program-counter, and the ROM responds by supplying its corresponding data-item as branch-address.

However, the ROM's data-width (32 bits) is more than that of a branch-address (16 bits).

The first 16 bits of each data-item form the branch-address, and the last 16 bits are used as RAM-address.

In other words, the CPU doesn't address the RAM itself. Instead, each 32-bit program-instruction (ROM data-item) contains a RAM-address to be used in that instruction. The RAM is thus addressed by the ROM instead of the CPU.

The addressed data-bit in RAM is made available to the CPU at its data-channel, labeled D.

A consequence of this scheme is that Qibec doesn't support computed addresses: there's no way to access other RAM-locations than those embedded in program-instructions.