Dynamic behaviour: introduction
To get a better understanding of how the CPU operates internally, it can be useful to look at what happens when.
During each instruction-cycle, subsystems take turns performing miniature tasks. The following text looks at what drives each subsystem, and the sequence of activities involved in executing an instruction.
(In the following figures, activities and involved subsystems are highlighted.)
If necessary, refer back to the section about the CPU's subsystems for information on each subsystem's function.
As seen from the outside, an external clock-signal has to be applied to the CPU in order for it to operate.
This clock-signal can be considered a square-wave with duty-cycle of 50%. (In other words, the signal is high for a given duration, then goes low for that same duration, then high again, etc.)
Inside the CPU, this clock-signal is split up into 4 "phase"-signals (phase 0 to 3). To get an idea of what this looks like, consider 4 consecutive pulses coming in on the CPU's clock-input.
The first pulse would cause (only) phase-signal 0 to emit a pulse. The second, third and fourth pulses on the clock-input would cause phase-signals 1, 2 and 3 to emit a pulse in turn. A fifth pulse coming in on the clock-input would again cause phase-signal 0 to emit a pulse, and so on.
Thus, each 4 consecutive pulses coming in on the clock-input are converted to 4 separate phase-signals, each emitting a pulse in turn. Each of these phase-signals activates one or multiple subsystems, resulting in ordered activities.
(In the current CPU-implementation, the 4th phase-signal is not used. The following text explains what happens during the first 3 phase-pulses.)
Phase 0 - latch data-channel
At the start of each instruction-cycle, consider the data at each I/O-channel (program-counter, branch-input and data-channel) to be stable.
Furthermore, the CPU's write-output, connected to the RAM's write-input, is inactive, so that the RAM supplies instead of receives data.
Phase-signal 0 is directly connected to the enable-input of the data-latch. Therefore, as first step of executing an instruction, the incoming value on the data-channel is latched.
That is, once the pulse on phase-signal 0 has passed, the outputs of the data-latch will reflect the data-channel's value at the time it was latched, regardless of whether the data-channel changes afterwards.
The multiplexer uses the non-inverted output Q of the data-latch to select between the next program-address and the branch-address. Since Q doesn't change anymore after phase 0, the multiplexer-selection can be considered constant as well from now on.
Phase 1 - invert data-channel
During this phase, the data-channel is written.
Phase-signal 1 is directly connected to the CPU's write-output. Therefore, during phase 1, the RAM is told to receive instead of supply data.
The data-channel is connected via a resistor to the inverted output of the data-latch, Q-overline.
This means that the data-channel now outputs the inverted value of whatever value it initially had. The RAM, being in write-mode, stores this inverted value.
Furthermore, the 1st address-latch is activated, so that the multiplexer-output "moves along" one step towards the program-counter.
(Revert back to the section about the CPU's subsystems for the reason behind 2 address-latches being used in between the multiplexer and the program-counter.)
Phase 2 - update program-counter
The last phase is less interesting: only the 2nd address-latch is activated, thereby updating the program-counter.
The program-counter thus effectively changes to the next logical program-address (current address plus one) or the supplied branch-address, depending on the multiplexer-selection.
As soon as this happens, the address-increment unit will see this new program-counter as input, and will output the incremented value to the multiplexer.
The address-latches prevent this value from "spinning around", as described in the section about the CPU's subsystems.
Switch to next program-instruction
After phase 2, the instruction-cycle is completed as far as the CPU is concerned.
The RAM-data has been inverted through the data-channel, and the CPU has picked a new program-address, now available at the program-counter output, selecting a new program-instruction in the ROM.
The first 16 bits of this instruction are made available to the CPU on its branch-input. The last 16 bits in turn select a new data-bit in the RAM, which is made available to the CPU at its data-channel.
(If necessary, revert back to the section about the address- and data-bus, and in particular the overview of a complete system with Qibec CPU, ROM and RAM.)
At this point, the CPU is ready to execute the new instruction - this will happen when a pulse is emitted on phase-signal 0.